Performance and energy efficiency of processing systems can be improved with efficient designs for memory subsystems. Conventional architectures for memory subsystems include a combination of non-volatile memory, such as static random access memory (SRAM), and volatile memory, such as dynamic random access memory (DRAM). SRAM and DRAM technologies are well known in the art.
SRAM cells are usually faster, but also larger than DRAM cells. Despite their expensive area consumption. SRAMs find a place on-chip in register files and caches, because of their higher speed and performance characteristics. However, SRAM cells tend to be leaky in nature and with shrinking device technology, the leakage problem of SRAM cells is exacerbated.
DRAM cells on the other hand, offer the advantages of small size or high density, at the cost of lower speeds. DRAM is conventionally used in main memory which can be located off-chip. DRAM is also lower cost, and can lend itself well to stacked architectures for creating large low-cost off-chip storage solutions. However, DRAM also suffers from limited scalability with shrinking device technology, especially in sub 10 nm range. Another well recognized disadvantage of DRAMs is their volatile nature, which requires constant refreshing, and thus incurring undesirable costs associated with refresh power.
Accordingly, conventional memory subsystem designs which employ performance-oriented SRAMs for on-chip caches and density-oriented DRAMs for off-chip memory suffer from limitations. Recent trends in processing system designs are placing high demands on on-chip last-level cache (LLC). Thus, SRAM LLCs are tending to occupy large areas on-chip, where the available real estate is constantly shrinking with ever-increasing components and shrinking overall surface area. On the other hand, applications with higher data access requirements are also placing additional stress on off-chip DRAM employed in main memory. However, DRAM is not well suited for delivering such higher bandwidth, as discussed above. Furthermore, off-chip interconnects between on-chip processors and off-chip memory, are also stressed more severely to meet increasing demands on bandwidth and this is also leads to increased power consumption.
Accordingly, there is a need in the art for memory subsystem designs which overcome the aforementioned problems associated with conventional designs.